• KSII Transactions on Internet and Information Systems
    Monthly Online Journal (eISSN: 1976-7277)

A Real-Time Histogram Equalization System with Automatic Gain Control Using FPGA

Vol. 4, No.4, August 27, 2010
10.3837/tiis.2010.08.011, Download Paper (Free):

Abstract

High quality camera images, with good contrast and intensity, are needed to obtain the desired information. Images need to be enhanced when they are dark or bright. The histogram equalization technique, which flattens the density distribution of an image, has been widely used to enhance image contrast due to its effectiveness and simplicity. This technique, however, cannot be used to enhance images that are either too dark or too bright. In addition, it is difficult to perform histogram equalization in real-time using a general-purpose computer. This paper proposes a histogram equalization technique with AGC (Automatic Gain Control) to extend the image enhancement range. It is designed using VHDL (VHSIC Hardware Description Language) to enhance images in real-time. The system is implemented with an FPGA (Field Programmable Gate Array). An image processing system with this FPGA is implemented. The performance of this image processing system is measured.


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Cite this article

[IEEE Style]
Junguk Cho, Seunghun Jin, Key Ho Kwon and Jae Wook Jeon, "A Real-Time Histogram Equalization System with Automatic Gain Control Using FPGA," KSII Transactions on Internet and Information Systems, vol. 4, no. 4, pp. 633-654, 2010. DOI: 10.3837/tiis.2010.08.011

[ACM Style]
Cho, J., Jin, S., Kwon, K. H., and Jeon, J. W. 2010. A Real-Time Histogram Equalization System with Automatic Gain Control Using FPGA. KSII Transactions on Internet and Information Systems, 4, 4, (2010), 633-654. DOI: 10.3837/tiis.2010.08.011